FM: A cheap RAM disk for LSI-11 Andrew Stewart, Mad Hobbyist and DECaholic ABSTRACT The major design goal of this project was to modify an MSV11 memory board, 64 Kbytes maximum, into a 0.5 or 1 Mbyte memory board that used a control register to map small segments of memory into the Qbus I/O page. The secondary goals were to be cheap, and create a bootable device handler for an LSI-11/2 machine running floppy disks and the RT-11 operating system. This would give the hobbyist the performance of the VM device (RT-11 RAM disk using KT-11 memory mapping) for a very low cost. This paper details the trade offs to achieve these goals. The result is a RAM disk that can be used with any Qbus processor. Why a RAM disk? A "RAM Disk" is a general term to describe a secondary storage device, such as a disk, that uses a primary storage technology, such semiconductor memory. The major benefit of such a device is very fast access to data. Conventional disks have delays whist the head(s) are moved across the disk (Seek time) and whilst the disk turns until the required data can be read (Rotational latency). On a RAM disk, any block of data can be read or written in the same time as any other block of data. The drawback is that semiconductor RAM memory loses its contents when power is removed. A RAM disk is normally loaded from a conventional disk when the system is powered up and any modified data is written back before the system is powered down. RAM Disks for LSI-11s The LSI-11 can only directly address 64 kilobytes (Kb) of memory. The LSI-11/23 and LSI-11/73 use memory mapping hardware to address upto 4 Megabytes (Mb) of memory. The RT-11 operating system can use the memory above 64 Kb as a RAM disk using the VM device handler. There are RAM disks available from third party manufacturers that can be used with the LSI-11. These use control and address registers to transfer data to and from the RAM disk. (1), (2) Unfortunately, these options cost money. Being hobbyist, the author decided to design and build a cheaper version. Not being a hardware or machine code wizard, two other people were called in. Hardware design is by Tom Evans and the RT-11 handler was designed by Ian Evans. No relation, just two brilliant friends. QBus boards cost a fortune, mainly because the market will bear it. Rather than design a new circuit board, it was decided to modify an existing memory board. 95% of the work is already done and, by selecting a superceeded board design, should be available cheaply. The MSV11-D board was chosen as a basis mainly because the author had the circuit diagrams for it and several boards were given to him. MSV11-D Memory Layout The MSV11-D may contain 8, 16, 32 or 64 Kb addressable on a 8 Kb boundary anywhere within the first 256 Kb of memory. Please note that the MSV11-D may be used in an 16 or 18 bit backplane. Not all the Qbus address bits are decoded on this board, so do not use it in a 22 bit backplane. The MSV11-D memory board divides memory into high and low two banks, and high and low bytes. Address bit 0 selects which byte is selected. The high and low banks are selected by logic on the board. 8 Kb and 32 KB boards have only the low bank whilst 16 Kb and 64 kb boards use both banks. See the right hand side of Figure 1. The semiconductor RAM chips used in the MSV11-D memory board are of two types: the 4096 x 1 bit chip or the 16384 x 1 bit chip. The former is used in 8 Kb and 16 Kb boards whilst the latter is used in 32 Kb and 64Kb boards. These memory chips use a technique called multiplexing to reduce the number of pins required for selecting an individual bit. The address is broken into 2 parts called row and column, and these parts are applied one after the other to select a bit. The 4096 x 1 bit chip multiplexes 12 bits onto 6 address pins and the 16384 x 1 bit chip multiplexes 14 bits onto 7 address pins. Addressing the FM RAM disk If you know your powers of 2 table, you will know that 14 bits are needed to address 16 Kb of memory, 16 bits are needed to address 64 Kb of memory and 20 bits are needed to address 1 Mb of memory. Locating the FM RAM disk in the I/O page means address bits must be supplied from another source other than the Qbus address lines. Analysis of the way the MSV11-D memory board supplies the row and column addresses to the memory chips lead to the decision to latch (store) 12 bits in a control register and supply the other 8 bits from the Qbus address lines. This method of addressing is called memory mapping. It is similar to the means that the LSI-11/23 and LSI-11/73 processor boards address more than 64 Kb. MSV11-D address decoding The MSV11-D memory board uses a PROM (programmable read only memory) chip to select the starting address. The Qbus signal "BANK 7 SELECT" must be at logic level Zero to enable the PROM. This stops the MSV11-D board responding when the I/O page is addressed. 5 Qbus address lines (BDAL 17, 16, 15, 14 and 13) and the values from 5 switches are used as the 10 input address bits of the PROM. The output of the PROM, 4 bits wide, are jumpered into the "MEMORY SELECTED" logic and the "BANK SELECT" logic. See the top left hand side of Figure 1. The contents of the PROM are cunningly encoded so that one particular output means that the Qbus address exactly matches the 5 switches. That is, the Qbus address is within the first 8 Kb of the memory board. The other three outputs signal whether the Qbus address is within the first 16 Kb, 32 Kb and 64 Kb respectively. For example, a 64 Kbyte board has the 64 Kb signal jumpered into the "MEMORY SELECTED" logic and the 32 Kb signal jumpered into the "BANK SELECT" logic. In contrast, a 32 Kbyte board has the 32 Kb signal jumpered into both the "MEMORY SELECTED" logic and the "BANK SELECT" logic. FM address decoding The first change was to invert the Qbus signal "BANK 7 SELECT" before it was supplied to the PROM. This now makes the FM board respond when the I/O page is addressed. 5 different Qbus address lines (BDAL 12, 11, 10, 9 and 8) were put into the PROM. The outputs of the PROM now signal whether the Qbus address is within 256 bytes, 512 bytes, 1 Kb and 2 Kb of the starting address of the FM board. Only the first two outputs were used. The 512 Byte output was used as a device select signal and was supplied to the orignal "MEMORY SELECT" logic. The 256 Byte output was used to select whether the control register or the Buffer was addressed. Figure 2 shows how the 20 bits for a 1 Mb address is generated in the FM RAM disk. Address bit 0 still selects the high or low byte. The high and low banks are now selected directly from address bit 7. 12 bits come from the CSR latch and 6 bits from the address bus. From the programming point of view, the FM RAM disk occupies 512 bytes, 256 words, of address space. There are 128 copies of the Control and Status Register (CSR) and 128 words, 256 bytes, of memory. This memory is known as the Buffer. The main reason that so much address space is wasted on the CSR is that it reduces the amount of extra logic required to more fully decode the CSR. LSI-11/2 systems tend to have very few devices and the I/O page tends to be sparsely populated. FM Control and Status Register The FM board uses 262,144 x 1 bit semiconductor RAM chips. These have 9 multiplexed address bits. The MSV11-D board has 2 octal (8 bit) latch chips to store 12/14 bits. These chips supply the 6/7 bits of row and column address bits to the 4096/16384 x 1 bit memory chips. The unused input to each octal chip are hard wired to the logic Zero state. Rather than try to free the eighth bit, two more octal latches of the same type are added to supply 2 extra bits for the row (high) address and to supply 3 extra bits for the column (low) address om each chip. The input enable for these two new chips and for the existing 7 bit row (high) address bit latch were rewired to be enabled, that is the data is stored, when the Control and Status Register (CSR) is written. 12 bits, from bit 15 to bit 4, are latched. The existing column (low) address chip continues to be supplied directly from the Qbus address bits when the memory of the FM board is selected. The seventh bit of said latch was disabled so Qbus signal BDAL7 provides the FM memory bank select signal. This means a 1 Mb RAM disk has a buffer size of 256 bytes and a 0.5 Mb RAM disk has a buffer size of 128 bytes. When the CSR is read, the contents of the Parity Error Latch is read as bit 15. During a read operation on any word or byte of the FM Buffer, any parity error will be remembered. This bit is cleared when the CSR is written. Normal programming means that after the CSR is loaded with the high address, all words of the Buffer are read then the CSR is read to see if any parity error occured. Locating FM in the I/O page. The next decision was to pick a standard address for the FM device. A block of 256 words on a 256 byte boundary must be reserved in the I/O page. The suggested address range for non DEC devices is betwwen 160000 and 167777. However, many memory boards can be configured to have memory in this range, thus giving a 60 Kb memory on LSI-11/2 systems. An extra 4K bytes may not sound much but try running Adventure on an FB system without it! Careful reading of the standard addresses DEC devices use in the range 170000 to 177777 revealed that the UDC-11, a Unibus device, occupied the 256 word address range 171000 to 171777. Since the FM RAM disk will only be used on the Qbus, that address range was selected. Note that the FM RAM disk may be located anywhere in the I/O page on a 128 word boundary. It is suggested that it be located in the above address range or on a 256 word boundary in the address range 160000 to 167777. There is no interrupt vector. The FM RAM disk should work with any Qbus processor. Building the FM RAM disk. A companion document which will probably appear with this paper on the 1987 Australian RT-11 SIG tape gives a step by step account of what tracks to cut, where to mount chips and the wiring required. WARNING! It is a long and involved process that requires a fine tipped temperature controlled soldering iron and Nerves of Steel. Not to be attempted by novice solderers. The stages in the project are: 1/ Create the FM address decoding modifications. 2/ Test the board as a very small FM RAM disk. 3/ Put in the 256K bit RAM Chips. Operation of the FM RAM disk. When the FM RAM disk is first powered up, the semiconductor RAM chips come up in a random state with a high probability that some words will give parity errors when read. This prevents the FM device from being initialised. "Formatting" the FM device consists of writing zeroes to every word. The FMAT program simply opens FM: as a file and writes blocks until it tries to write to a block number higher than the last available block. The FM device handler for RT-11 can be used with the Single Job (SJ) and Foreground/Background (FB) monitors. There are versions for the Extended Memory (XM) monitor and for the RT-11 compatible operating system TSX. To gain the best out of the FM Ram disk, it is suggested that the startup command file on the boot disk format and initialise the FM device then copy all relevant RT-11 system and utilities to the FM device. A different command file is copied as the startup command file and the FM device be booted. Performance Testing Results. Testing was done on a RT-11 v5.4a FB system with 256 Kb of memory. LSI-11/23 and LSI-11/2 processors were swapped in as necessary. The first test was to compare the VM and FM devices. A command file was run that showed the time before and after 10 DIR/BAD commands on a 392 decimal block device created on both devices. The FM device was slightly faster, but this would depend on the memory used. The second test was to compare reading 1 Mb of data on both processors. There was a 250 Kb/sec transfer rate on the LSI-11/23 and 170 Kb/sec transfer rate on the LSI-11/2. This means you can expect the read and write rate of the FM RAM disk in an LSI-11/2 system to be comparable to a good winchester disk subsystem. Conclusion For small floppy based systems, it effectively gives another device that is fast, quiet and cheap. The design was an exercise in minimising extra logic and kept the author off the streets (much appreciated by other residents of Richmond, especially during the nights of the Full Moon!). From the marketing point of view, the project is about two years too late. MSV11-D memory boards were easier to come by, and people had not quite given up on the old dual floppy 64K byte systems. Acknowledgements Tom Evans must take all credit for the hardware design. Initially, he was a little reluctant to get involved in the project which was fine by the author. I wanted to gain experience in hardware design. Once Tom had started to advise the best route, the project fired his imagination and I couldn't keep up! Ian Evans did the initial design for the FM handler using the VM device as a starting point. He and Tom had a 9 hour marathon debugging effort at my house that produced a bootable handler! References (1) 1986 DECUS Europe Symposium Proceedings, page 491, "SM, A RAM disk for the Q-Bus" (2) HARDCOPY, May 1987, pages 87 to 92, 3 articles under the heading "Performance Enhancements"