
module top;
   reg clk;
   reg [0:1] in1;
   reg [0:1] in2;
   wire [0:1] o1;
   wire [0:1] o2;

   vdff m1 (o1, in1, clk);
   vdff m2 (o2, in2, clk);

endmodule

module vdff (out, in, clk);
   parameter size = 2, delay = 1;
   input [0:size-1] in;
   input clk;
   output [0:size-1] out;
   reg [0:size-1] out;

   always @(posedge clk)
      # delay out = in;
endmodule

