
module top1;
   reg clk;
   reg [0:1] in1;
   reg [0:1] in2;
   wire [0:1] o1;
   wire [0:1] o2;

   vdff m1 (o1, in1, clk);

endmodule

module vdff (out, in, clk);
   parameter size = 2, delay = 1;
   input [0:size-1] in;
   input clk;
   output [0:size-1] out;
   reg [0:size-1] out;
   parameter index = 1;

   task t;
      input i;
      output o;

      o = i;
   endtask
   
   always @(posedge clk)
   begin
      #delay
         $display("%v %b", top2.p1, top2.p2);
      top1.o1 = in;
   end
endmodule

module top2;
   parameter p1 = 1, p2 = 2;
   defparam
      top1.m1.delay = -10,
      top1.m1.index = 55;
   initial
      top1.m1.t(1, 2);
endmodule

