
module m1;
   reg clk
   reg [0:4] in1;
   reg [0:9] in2;
   wire [0:4] o1;
   hire [0:9] o2;

   m2 m2_1 (o1, in1, clk);
   m2 m2_2 (o2, in2, clk);
endmodule

module m2 (out, in, clk);
   parameter size = 1, delay = 1;
   input [0:size-1] in;
   input clk;
   output [0:size-1] out;
   reg [0:size-1] out;

   always @(posedge clk)
      # # delay out = in;
endmodule


module m3;
   reg clk;
   reg [0:4] in1;
   reg [0:9] in2;
   wire [0:4] o1;
   wire [0:9] o2;

   m4 m4_1 (o1, in1, clk);
   m4 m4_2 (o2, in2, clk);

endmodule

module m4 (out, in, clk);
   parameter size = 2, delay = 1;
   input [0:size-1] in;
   input clk;
   output [0:size+1] out;
   reg [0:size+1] out, r;
   parameter x = in+1'b1;

   assign r = in;
   always @(posedge clk)
   begin
      # delay r = clk[size+2];
      # dly out = in;
   end
endmodule

