/*	Copyright (c) 1984, 1986, 1987, 1988 AT&T	*/
/*	  All Rights Reserved  	*/

/*	THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF AT&T	*/
/*	The copyright notice above does not evidence any   	*/
/*	actual or intended publication of such source code.	*/

#ident	"@(#)head.sys:pic.h	1.5"

/* Definitions for 8259 Programmable Interrupt Controller */

#define PIC_NEEDICW4    0x01            /* ICW4 needed */
#define PIC_ICW1BASE    0x10            /* base for ICW1 */
#define PIC_86MODE      0x01            /* MCS 86 mode */
#define PIC_AUTOEOI     0x02            /* do auto eoi's */
#define PIC_SLAVEBUF    0x08            /* put slave in buffered mode */
#define PIC_MASTERBUF   0x0C            /* put master in bnuffered mode */
#define PIC_SPFMODE     0x10            /* special fully nested mode */
#define PIC_READISR     0x0B            /* Read the ISR */
#define PIC_NSEOI       0x20            /* Non-specific EOI command */

#define PIC_VECTBASE    0x40            /* Vectors for external interrupts */
					/* start at 64.                    */
/*
 * Interrupt configuration information specific to a particular computer.
 * These constants are used to initialize tables in modules/pic/space.c.
 * NOTE: The master pic must always be pic zero.
 */

#if defined (MB1) || defined (MB2)

#define NPIC    2                       /* 2 PICs */
/* Port addresses */
#define MCMD_PORT       0xC0            /* master command port */
#define MIMR_PORT       0xC2            /* master intr mask register port */
#define SCMD_PORT       0xC4            /* slave command port */
#define SIMR_PORT       0xC6            /* slave intr mask register port */
#define MASTERLINE      0x07            /* slave on IR7 of the master PIC */
#define SLAVEBASE       ((MASTERLINE+1)*8) /* slave IR0 interrupt number */
#define PICBUFFERED     1               /* PICs in buffered mode */

#endif /* MB1 or MB2 */

#ifdef	AT380		/* additional defines for the 82380 */

/*
 * In an 82380, banks B and C are treated as the master and slave
 * respectively. None of the interrupts on Bank A are used directly
 * except for IRQ2 which just cascades from banks B and C.
 */

/* Port Addresses for Bank A */
#define ACMD_PORT       0x30            /* bank A command port */
#define AIMR_PORT       0x31            /* bank A intr mask register port */

/* Vector Registers */
#define	VRA0		0x38		/* Bank A vector registers */
#define	VRA1		0x39
#define	VRA1_5		0x3a
#define	VRA3		0x3b
#define	VRA4		0x3c
#define	VRA7		0x3f

#define	VRB0		0x28		/* Bank B vector registers */
#define	VRB1		0x29
#define	VRB3		0x2b
#define	VRB4		0x2c
#define	VRB5		0x2d
#define	VRB6		0x2e
#define	VRB7		0x2f

#define	VRC0		0xa8		/* Bank C vector registers */
#define	VRC1		0xa9
#define	VRC2		0xaa
#define	VRC3		0xab
#define	VRC4		0xac
#define	VRC5		0xad
#define	VRC6		0xae
#define	VRC7		0xaf

#endif /* AT380 */


#ifdef AT386            /* AT386 board */

#define NPIC    2                       /* 2 PICs */
/* Port addresses */
#define MCMD_PORT       0x20            /* master command port */
#define MIMR_PORT       0x21            /* master intr mask register port */
#define SCMD_PORT       0xA0            /* slave command port */
#define SIMR_PORT       0xA1            /* slave intr mask register port */
#define MASTERLINE      0x02            /* slave on IR2 of master PIC */
#define SLAVEBASE       8               /* slave IR0 interrupt number */
#define PICBUFFERED     0               /* PICs not in buffered mode */

#endif /* AT386 */
