A symbolic language data processing system comprises a sequencer unit, a data path unit, a memory control unit, a front-end processor, an I/O and a main memory connected on a common Lbus to which other peripherals and data units can be connected for intercommunication. The system architecture includes a novel bus network, a synergistic combination of the Lbus, microtasking, centralized error correction circuitry and a synchronous pipelined memory including processor mediated direct memory access, stack cache windows with two segment addressing, a page hash table and page hash table cache, garbage collection and pointer control a close connection of the macrocode and microcode which enables one to take interrupts in and out of the macrocode instruction sequences, parallel data type checking with tagged architecture, procedure call and microcode support, a generic bus and a unique insruction set to support symbolic language processing.

Current U.S. Class:	711/216; 707/206
Intern'l Class:	G06F 009/00

                  TABLE 1
    ______________________________________
    Microcode Control of Sequencer
    ______________________________________
    U SEQ <1:0>
    0 no function
    1 pushj (i.e. increment CSP)
    2 dismiss current task
    3 popj (i.e. decrement CSP)
    This field is effectively forced to 0 when the sequencer is stopped,
    and forced to 1 when a trap or slow jump is taken.
    U CPC SEL <1:0>
    Selects address from which next microinstruction will be taken,
    except for bit 12 which may be selected from -COND (skip).
    0 NAF (next-address-field of current instruction)
    1 CTOS (control-stack or IFU, normally used together with POPJ)
    2 NPC (take-dispatch, restore from trap)
    3 (spare)
    A trap or slow jump supplies an address and ignores this field.
    U NPC SEL
    Selects source for loading NPC register.
    Normally:
    0 NAF modified by dispatch in bits 11:8
    1 NEXT CPC + 1 (only the low 8 bits increment)
    With SPEC NPC SEL 1 and MAGIC = 3 (or 0 on rev-3 board).
    0 CTOS (restore from trap)
    1 CPC (forced when taking trap or slow jump)
    U NAF <13:0>
    Next-address field
    These fields also used by data-path:
    U COND FUNC <1:0>
    0 nothing
    1 SKIP (CMEM A 12 gets -COND)
    2 (TRAP IF COND)
    3 (TRAP IF -COND)
    U SPEC <4:0>
    30 ARITHMETIC TRAP WITH DISPATCH
    (If trap to address in NAF, bits 11-8
    get replaced by high type bits of Abus and Bbus.)
    31 HALT
    Stops the machine after executing this microinstruction.
    32 NPC MAGIC
    Modifies U NPC SEL above, also allows connection between the
    data path and the sequencer (see MICROINSTRUCTION.BITS).
    33 AWAKEN TASK
    Set wakeup for software task selected by U MAGIC <1:0>
    34 WRITE TASK
    Write task memory from address and data on Obus.
    35 TASK DISABLE
    Forces the current task to be the same in the cycle after
    next as in the next cycle. Because of this pipelining, you
    need to do this function twice in a row before it really
    takes effect.
    ______________________________________

                                      TABLE 2
    __________________________________________________________________________
    DWTS
        State
           CTDS
               CUR TASK
                      NEXT TASK
                              Capture
                                  OPC
                                     NOP
                                        Error
    __________________________________________________________________________
    --  clk
           clk clk    clk >=  clk clk
                                     no clk
    D---
        clk
           clk clk    clk <   clk clk
                                     no clk
    W---
        hold
           clk hold   clk >=  no  clk
                                     yes
                                        clk
    DW--
        hold
           clk hold   clk >=  no  clk
                                     yes
                                        clk
    T-  clk
           clk clk    clk >=  clk clk
                                     yes
                                        clk
    D-T-
        clk
           clk clk    hold    clk clk
                                     yes
                                        clk
    WT- hold
           clk hold   clk >=  no  clk
                                     yes
                                        clk
    DWT-
        hold
           clk hold   hold    no  clk
                                     yes
                                        clk
    S   clk
           clk clk    hold    clk clk
                                     no clk
    D--S
        clk
           clk clk    clk =   clk clk
                                     no clk
    W-S clk
           clk clk    hold    no  clk
                                     yes
                                        clk
    DW-S
        clk
           clk clk    hold    no  clk
                                     yes
                                        clk
    TS  clk
           clk clk    hold    clk clk
                                     yes
                                        clk
    D-TS
        clk
           clk clk    hold    clk clk
                                     yes
                                        clk
    WTS clk
           clk clk    hold    no  clk
                                     yes
                                        clk
    DWTS
        clk
           clk clk    hold    no  clk
                                     yes
                                        clk
    __________________________________________________________________________
     DISMISS = (task voluntarily going away, after 1 (or 2) more
     microinstructions)
     W = MC WAIT (NOP this microinstruction and try it again, on demand of
     memory control)
     T = Trap (Doublelength cycle, NOP this microinstruction, take different
     successor)
     S = TASK SWITCH (next microinstruction from different task)
     State = UIR, NPC, CPC, CSP
     Capture = taskstate capture registers
     Error = hardware error registers

    ______________________________________
    0 RUN         Set to 1 to let the machine run freely
    1 STEP        Set to 0 then to 1 to clock the machine
                  once
    2 ENABLE DP   If 0, STEP doesn't affect the data path
    3-ENABLE SQ   If 1, STEP and RUN don't affect the
                  sequencer except UIR
    4 ENABLE CHEM If 1, UIR from CMEM,
                  else from CMEM WD register
    5 CHEM WRITE  If 1, write control-memory
    6 ENABLE TRAP If 1, trap conditions set nop and change
                  cmem address
    7 ENABLE ERRHALT
                  If 1, parity error will inhibit RUN
    8 ENABLE TASK If 1, enables task scheduling, if 0 the
    9-12 TASK     task number is forced from these bits
                  here
    13 ENABLE WP  Enable write-pulse to task and control-
    14            stack memories spare
    15            spare
    ______________________________________

                  TABLE 3
    ______________________________________
    SPY WRITE CMEM0,1, . . .,13 WD
    Write an 8-bit slice of the CMEM WD register. This register
    is a source of write data for control-memory and also a source
    of microinstructions into UIR when cmem is disabled.
    SPY READ CMEM0,1, . . .,13
    Read an 8-bit slice of UIR (which typically contains data from
    CMEM).
    SPY WRITE CTL1,2
    Write sequencer control & clock register described above.
    This has two spy functions since it is a 16-bit register; the
    CTL1 is the least-significant byte.
    SPY READ NEXT CPC (2 addresses)
    Read NEXT CPC lines, which are the control-memory address in the
    absence of tasking. Allows reading NPC, CTOS, trap address,
    U NAF,
    To read the CPC you must first
    single-step it into the NPC. To control the NEXT CPC selection you
    force a microinstruction into the UIR.
    SPY READ SQ STATUS (2 addresses)
    Read error halt conditions as a 16-bit word:
    7 AU STOP        15 -ERRHALT
    6 MC STOP        14 TSK-STOP
    5 BMEM PAR ERR   13 CTOS CAME FROM IFU
    4 AMEM PAR ERR   12 CMEM (UIR) PAR ERR
    3 PAGE TAG PAR ERR
                     11 TASK MEM PAR ERR
    2 TYPE MAP PAR ERR
                     10 CTOS (LEFT) PAR ERR
    1 GC MAP PAR ERR 9 CTOS (RIGHT) PAR ERR
    0 (spare)        8 MICROCODE HALT
    SPY READ TASK
    <3:0> are CUR TASK
    SPY READ SQ STATUS2
    More status:
    1-0 are the CTOS parity bits
    SPY READ SQ BOARD ID
    Read the board-ID prom (gives serial number, ECO level, etc.)
    Address comes from the U AMRA <4:0> field of UIR
    SPY READ DP BOARD ID
    Read the board-ID prom on the datapath board (the spy address
    is decoded by the sequencer).
    SPY READ OPC1,2
    Reads PC history memory.
    This is a 16 entry RAM where each entry contains a PC in bits
    NOP for that microinstruction, and bit
    <15> = 1 if the next microinstruction came from a different task.
    The OPC memory reads out backwards (i.e. with the sequencer
    stopped, the first read gets you the last instruction executed, the
    next read gets you the instruction before that, etc.) After 16 reads
    it is back in its original state
    Because you can only read this one byte a time (reading either byte
    decrements the address counter) you have to first read all 16 even
    bytes and then read all 16 odd bytes).
    ______________________________________

    ______________________________________
    LBUS ADDR 23:19
                    the physical page to be accessed
                   next.
    NORMAL ACTIVE L
                   true if this is an active cycle and
                   the page tags are supposed to see
                   it.
    LBUS STATE CLK L
                   the clock gated by LBUS WAIT.
    DP SET CG TAG L
                   true during an active cycle if the
                   datapath output during the previous
                   cycle was a pointer and its address
                   was in a temporary space. If this
                   active cycle is for a virtual
                   write, the GC tag bit needs to be
                   set.
    WRITE ACTIVE L true during an active write cycle
                   (registered version of LBUS WRITE
                   L).
    WRITE PAGE TAG L
                   true if lbus-dev-write of the
                   page tag being done.
    READ PAGE TAG L
                   true if reading page tag
                   (via lbus-dev-write).
    LBUS DEV 4:3   modifiers for the above.
    ______________________________________
     Note:
     the spec and magic fields could be used instead of the microdevice I/O.

    ______________________________________
    LBUS DEV COND L   Asserted when READ PAGE
                     TAG and the selected tag
                     bit is set.
    PAGE TAG PAR ERR L
                     asserted when bad parity
                     is read from the page
                     tags.
    ______________________________________

    ______________________________________
    0                the gc tag bit
    1                the referenced bit
    ______________________________________

    ______________________________________
    00                the gc tag bit
    01               the referenced bit
    10               the parity bit
    11               (not used)
    ______________________________________

    ______________________________________
    BK ABUS      35:0 - bidirectional extension of the data
                 path's Abus. This is used to read VMA,
                 PC, map, and memory (or bus) data into
                 the data path, and to emit physical
                 addresses from the data path. Bits 31-0
                 are bidirectional, but bits 35-32 are
                 unidirectional, they always go from the
                 memory control to the data path; this
                 allows the cdr code of a memory location
                 to be merged into the data to be stored
                 into it, which needs to be on the Abus
                 so it can get to the type and gc maps.
                 The parity bits on the internal Abus do
                 not connect to the MC.
    LBUS 35:0    the main data bus. The data path can
                 drive this either directly or through a
                 register. This is used when writing main
                 memory, when writing the bus, and when
                 writing registers on the MC board. The
                 error-correction bits do not connect
                 to the DP.
    LBUS ADDR 11:0
                 physical memory address into the data
                 path. This is used when a supposed main
                 memory access actually refers to internal
                 A memory. See below.
    MC OBUS TO   DP result from this cycle drives LBus.
    LBUS L
    MC OBUS REG  DEP result from last cycle drives
    To LBUS L    LBUS
    GC TEMP L    to GC page tag bits. If this is asserted at
                 the end of a cycle which writes into main
                 memory, then during the following cycle,
                 which is when the write actually happens,
                 the GC page tag bit for the page being
                 written into its turned on.
    MC ADDR IN   Asserted if the last memory address
    AMEM L       selected by this task (need only work for
                 emulator) points at A-memory. The data
                 path uses this to enable A-memory instead
                 of BK ABUS for memory reads, and to
                 enable A-memory writing for memory
                 writes. See below.
    ABUS OFFBOARD
                 Asserted if the BK ABUS is an input to
    L            the data path. The DP drives the BK
                 ABUS whenever it isn't receiving it.
    SEQUENCE     Tells the IFU to generate a bogus
    BREAK        instruction to take the sequence break
                 (macrocode interrupt).
    ______________________________________

                                      TABLE 4
    __________________________________________________________________________
    MEMORY AND CLOCK SIGNALS. (From <LMIFU>MC.)
    The bus is used in three ways; accessing memory, accessing I/O device
    registers which look like memory, and accessing "MicroDevices"
    MicroDevices are distinguished because they are addressed by a
    separate 10-bit field which comes directly from the microcode, and do
    not follow the 3 cycle Request/Active/Data protocol of memories. One
    example of such a device is a DMA device such as the disk; the DMA
    task microcode commands the disk to put data onto the bus or take it
    off, while doing a memory cycle. We'll call the three classes
    of responders "Memory, MemoryDevices, and MicroDevices."
    All transactions on the L-bus are synchronous with the system clock.
    For example, memory responds to requests with a 2 or 3 cycle
    sequence, viz:
    On the first cycle (Request), the processor puts an address on LBUS
    ADDR, puts the type of cycle on LBUS WRITE, and asserts LBUS
    REQUEST. All the memory cards compare the high bits of the LBUS
    address with their slot number. The selected memory card drives the
    row address onto the RAM address lines, and at the leading edge of
    LBUS CLOCK starts RAS. After a delay it muxes the column address
    onto the RAM address lines, and finally at the clock boundary CAS is
    enabled.
    The second (Active) cycle is used to access the RAM: on a read the
    RAM output is strobed into a latch at the end of the cycle; on a
    write, the bus has the write data and ECC bits and the RAM WE is
    driven by a gated Lbus Clock (late write operation). RAS and CAS
    are reset at the end of this cycle.
    During the third (Data) cycle, the latched read data is driven on
    the bus (during First Half), the RAM chips precharge during their
    RAS recovery time, and possibly a new Request cycle occurs.
    The bus clock is designed so that the memory card can start RAS with the
    leading edge and star CAS with the trailing edge and be guaranteed of
    meeting the RAM timing specs. No other use is intended for the leading
    edge of clock. It is suggested that MemoryDevices initiate response
    to requests at the trailing edge of clock.
    The clock seen by devices on the bus (LBUS CLOCK) is a version of the
    clock that drives the processor. Its frequency is roughly 5 Mhz but
    the exact period of each cycle may vary between 180-260 ns depending
    on the cycle length specified by the microcode. Although the
    processor controls the cycle length, LBUS CLOCK is unaffected by any
    clock inhibit conditions in the processor - operations on the bus
    proceed independently of the microcode, once they have been initiated.
    Memory data error-correction will also extend the clock for some
    period of time.
    An exception to this is when the processor takes a trap. In that case
    LBUS CLOCK is stretched - the extra time occurs in the second (or
    high) phase. While the main clock is held high, the clock and
    sequencer conspire to preform a second cycle internally that fetches
    the trap handler microinstruction. Because of this, two first-half
    clocks will happen for only one LBUS CLOCK. If the extended cycle is
    a Data cycle, the processor will latch the data seen during the first
    first-half.
    Note: The leading edge of FIRST HALF is >>not<< the same as the
    trailing edge of LBUS CLOCK. First-half is primarily intended as a
    timing signal that controls enabling data from memories onto the bus.
    The only other nefarious use you are allowed is to clock something
    with the mid-cycle edge of FIRST HALF, and then you should be prepared
    to see two of them on some cycles.
    A central Memory Control manages the state of the bus and arbitrates
    between requests from the processor, IFU, and FEP. Both Memory and
    MemoryDevices are expected to conform to the same timing protocol.
    [document FEP/MC arbitration].
    Any MemoryDevices (like the TV) that are unable to respond in 3 cycles
    must assert LBUS WAIT during the Active cycle until they can respond.
    The memory control state will proceed on the first Active cycle where
    LBUS WAIT is not asserted. LBUS WAIT should not be present on any
    other cycle, and must be developed early enough to propogate the
    length of the bus, go through a xcvr, and gate the clock. DMA devices
    also watch LBUS WAIT, so they know which cycle is the one that they
    should read or write the data.
    Block mode operations. In some cases the processor issues a series of
    requests on back-to-back cycles. This is called "block mode". A new
    request can be started each cycle. When a block-mode operation in
    underway, the bus is segmented into a 3-stage pipeline, one stage for
    addressing, one stage for ram access, and one stage for data transfer
    (on reads).
    The addresses of block mode requests are always in increasing
    sequential order, although any pattern that avoids referencing
    addresses [n, n+4] in adjacent cycle would be OK. The existing
    memory card interleaves on bits 18,1,0, so an individual ram always
    see at least 4 cycles between requests for sequential locations.
    MemoryDevices also have to handle block mode requests, because the
    microcode will not in general want to distinguish references to MOS
    memory from MemoryDevices. This means that the device must be
    prepared to accept a request during its "active" cycle. Request
    cycles are unconditional, there is no way for a device to reject or
    delay a request. The cycle following a request is the active cycle,
    which can be repeated (via LBUS WAIT) until the device is ready to
    accept data (on writes) or enter the data cycle (on reads).
    Bi-directional data bus, active high tri-state.
    LBUS <43:36> are the ECC bits. Driven by processor or FEP
    on write Active cycles. Driven by memories on read Data
    cycles. Also used to transfer data between processor and
    Devices. Also is used to carry the Obus signals from the data
    path card (E) to the other cards in the processor (I and C).
    Physical address. Tri-state driven from
    processor or FEP. A physical address of 24 bits is
    semi-consistent with allowing a maximum of 31 physical slots,
    each of which could hold 512K words of memory.
    Differential ECL system clock.
    differential ECL timing signal from memory control.
    Used during Data cycles to enable memory data onto the bus.
    The memory card drives data onto the bus during the first half
    of the cycle, the memory control reads the bus data and does
    error correction. During the second half cycle, the corrected
    data is driven on the bus from the memory control.
    Memories must insure that data is driven out on the bus as
    soon as possible after the leading edge of FIRST HALF, because
    the memory control needs most of the first half to decode the
    ECC syndrome.
    LBUS REQUEST L - Request for Memory or MemoryDevices addressed by
    Bus.Address. Stable by leading edge of Bus.Clock  enough
    time for address compare and 2 levels of logic.
    LBUS REQUEST L and LBUS WRITE L, along with the address, are
    asserted towards the end of the first cycle of a transaction.
    The data are transferred during the second or third cycle.
    The requests, write, and address lines are not valid during
    those cycles (indeed they may be used to start another transaction).
    LBUS WRITE L - from the processor or FEP. The write data will be
    driven onto the bus during the next cycle. Otherwise, the
    requested cycle is a read, and the memory will drive the bus
    during the 2nd succeeding cycle.
    LBUS WITH ECC - From Memories that don't have ECC bits. Driven during
    Data cycle.
    LBUS WAIT L - From MemoryDevices. Asserted for as many cycles as
    necessary to hold memory control in Active cycle state. Must
    be valid early in the cycle.
    LBUS REFRESH L - All dynamic RAM memories perform a refresh.
    All rows of memory refresh at once. The memory array bypass
    capacitors hold enough charge to supply the RAMs for the
    refresh cycle, so the transient shouldn't be seen by the power
    supply. The refresh timer and address counter is in the
    Memory Control, it has nothing to do with micro-tasking so
    that the memories will continue to get refreshed when the
    processor is being single stepped.
    LBUS ID REQUEST L - Requests that the selected board supply information
    about itself. The board selection is by matching
    LBUS ADDR <23:19> against the slot number (see below).
    LBUS <7:0> are driven with one of 32 bytes of data selected
    by LBUS ADDR <6:2>. The format of these data bytes is not
    yet specified, but generally includes the board type, board
    serial number, board revision level, and a checksum sensitive
    to failures of the data and address lines.
    Note that memory refreshing may take place, using LBUS ADDR
    <17:10>, while a board ID is being read using the other
    address lines. The PROM data should be driven onto the bus
    for as long as ID REQUEST is asserted. (The memory card is
    slightly strange in that it "buffers" LBUS ADDR <6:2> through
    the same latch that it uses to hold the column address during
    normal memory cycles. This latch is open during LBUS CLOCK,
    so the memory board doesn't produce correct data until the
    second cycle after ID REQUEST and LBUS ADDR are present. The
    FEP compensates for this, and other boards shouldn't
    necessarily emulate the memory card.
    SLOT NUMBERING
    a slot number built into the blackplane. These pins
    are grounded in a different pattern at each slot; if the board plugged
    into that slot provides pullups it will see a unique slot number.
    This is matched against LBUS ADDR <23:19> for Memory, MemoryDevice,
    and IDRequest operations, and against LBUS DEV <9:5> for MicroDevice
    operations, to select the desire board. LBUS SLOT <4> is actually
    bussed across each card cage, and is grounded in the main card cage
    and left floating in the extension cage. More discussion of this below.
    RESET SIGNALS
    LBUS RESET L - general reset line. This is brought low when power is
    turned
    on, and whenever the FEP feels like asserting it.
    LBUS POWER RESET L - brought low when power is not valid. This line is
    used
    to protect disks and to perform initializations only needed when first
    powering on. When the machine is powered up, this line is grounded and
    remains grounded until the FEP validates the power and cooling and turns
    it
    off. This line is also grounded before turning off the power.
    MICRODEVICE SIGNALS
    a device address from microdevice operations. Bits <9:5>
    select a board, by matching against the slot number. The special slot
    numbers 36 and 37 are used to select the FEP and MC boards,
    respectively.
    Bits <4:0> select a register or operation within the board.
    LBUS DEV READ L - commands the device to put data onto the Lbus data
    lines.
    LBUS DEV WRITE L - commands the device to take data from the Lbus data
    lines,
    at the LBUS CLOCK. Note that when LBUS DEV WRITE is used to inform the
    device
    of a DMA memory cycle being started, the Lbus data lines contain
    unrelated
    data perhaps associated with an unrelated memory read. LBUS DEV WRITE L
    should
    only be depended upon at the clock edge; it should not be used to gate
    the clock.
    If the microinstruction doing the microdevice write is NOPed by a trap or
    by
    a control-memory parity error (e.g. a microcode breakpoint), LBUS DEV



    WRITE L
    will be asserted for a period of time, past the leading edge of the
    clock, and
    will then be deasserted some time before the trailing (active) edge of
    the clock.
    LBUS DEV COND L - the selected device may ground this line (with an
    open-collector nand gate) to feed a skip condition to the microcode.
    Microdevice I/O is used for general communication with devices, for
    internal
    communication within the processor complex (including the FEP), and for
    control of DMA operations.
    For general communication with devices, the Lbus simply acts as an
    extension
    of the processor's internal bus. Data are transmitted within a single
    cycle
    and clocked at the trailing edge of the clock.
    Microdevice read and write to slot number 36 is used for communication
    with
    to FEP, the page tags, and the microsecond clock. Microdevice read and
    write to slot number 37 is used for communication with the MC and SQ
    boards. (It is used when reading and writing the NPC register in the SQ
    board in order to reserve the Lbus and connect it to the datapath; the
    control signals to the SQ board are transmitted separately.)
    DMA works as follows. The device reguests a task wakeup when it wants to
    transfer a word to or from memory. The microcode task wakes up for 2
    cycles. The first cycle puts the address on the Lbus address lines,
    makes
    a read or write request to memory, and also increments the address. The
    second cycle decrements the word count, to decide when the transfer is
    done. The microcode asserts DISMISS during the first cycle (the task
    switch occurs after the second cycle.) The device is informed of the DMA
    operation by the microcode through the use of a microdevice write during
    the first cycle. This microdevice write does not transfer any data to
    the
    device, but simply tells it that a DMA operation is being performed, and
    clears its wakeup request flag. (The wakeup request is removed from the
    bus immediately, and the flag is cleared at the clock edge.) For a read
    from device into memory, the device puts the data on the bus during the
    active cycle (one cycle after the microdevice write) and it is written
    into
    memory. For a write, the device takes data from the bus two cycles after
    the microdevice write.
    Some devices look like memory, rather than using microdevice I/O. The
    criterion for which to use is generally whether the device is operated
    by special microcodes, and the convenience and need for speed of that
    microcode.
    Devices that look like memory can be accessed directly by Lisp code.
    SPY SIGNALS
    an 8-bit, bidirectional, rather slow bus used for diagnostic
    purposes. Allows the FEP to read and write various cpu state while the
    machine is running.
    addresses the diagnostic register to be read or written
    SPY READ L - gates data from the selected register onto the spy bus.
    SPY WRITE L - clocks data from the spy bus into the selected register,
    on
    the trailing edge.
    SPY DMA SIGNALS
    When the spy bus isn't being used for diagnostics, the FEP uses it as a
    special side-door path to certain DMA devices. Normally the FEP uses it
    to receive a copy of all incoming network packets; it can also set it up
    to transmit to the network and to read from the disk (possibly also to
    write the disk; this is unclear and not yet determined). Details are
    in <LMHARD>DMA.DESIGN; that part of that file is said to be up to date.
    8 bits of data to or from DMA device. These lines are
    continuously driven during DMA operations; the FEP's DMA buffer does
    not latch them.
    SPY DMA ENB L - asserted if DMA operations are permitted to take place;
    deasserted if the spy is being used for diagnostic purposes.
    a clock, asseted by the device. On the rising edge of
    this a byte is transferred and the address is incremented. The device
    must take the data (for write) or supply the new data (for read) on or
    before the leading edge of this. This is the same wire as SPY ADDR 0.
    SPY DMA BUSY L - asserted if the DMA operation has not yet completed.
    This can be asserted by the device or the FEP or both, depending on who
    determines the length of the transfer. For example, for network input
    this comes from the device, while for network output and disk input
    it comes from the FEP (the disk doesn't know it's own block size).
    This is the same wire as SPY ADDR 1.
    Timing Requirements.
    LBUS RESET and LBUS POWER RESET are asynchronous. All other side-effects
    should take place at the trailing edge of the clock. LBUS REQUEST and
    the address lines are stable before the leading edge of the clock. LBUS
    WRITE
    however is only valid at the trailing edge of the clock; it can change
    as
    the result of a trap. Consequently it is illegal for memory reads to
    have
    side-effects, as memory reads not requested by the program can occur.
    In a microdevice write, the address lines (LBUS DEV 0-9) are stable
    throughout
    the cycle, however the data (LBUS 0-35) and LBUS WRITE itself are only
    valid
    at the trailing edge of the clock. The data lines are only driven during
    SECOND HALF.
    In a microdevice read, the address lines (LBUS DEV 0-9) are stable
    throughout the cycle, however LBUS READ itself is only valid at the
    trailing edge of the clock; side-effects are permitted but may only
    happen
    at the clock. The data (LBUS 0-35 or in some devices LBUS 0-31) should
    be
    driven throughout the cycle.
    TASK 8-15 REQ and TASK 4 REQ are asynchronous and may be driven at any
    time.
    Once a task is requested, it should stay requested until explicitly
    dismissed
    or until LBUS RESET. When a task is dismissed, the task request must be
    deasserted during the cycle that is dismissing, so that a new task of
    presumably lower priority can be scheduled. The task request flip flop
    however must not be cleared until the trailing edge of the clock, the
    time when all side-effects occur. During the cycle after a dismiss the
    task request will not be looked at by the processor, however the device
    should deassert its request as quickly as it can (a glitch is expected
    at the beginning of the cycle).
    Data driven onto the Lbus data lines (LBUS 0-43) must be synchronized to
    the processor clock; failure to observe this rule can cause every sort
    of
    internal parity error in the processor as well as memory ECC errors.
    When
    reading from memory, the data must be stable on the bus as early as
    possible, to allow time for the ECC-error decision before the end of
    FIRST
    HALF. Memory read data are driven onto the bus during FIRST HALF, and
    then
    latched by the processor during SECOND HALF. This latch is followed by a
    second one, that is opened during the middle of FIRST HALF to pick up
    the
    raw data, and again during the middle of SECOND HALF to pick up the
    ECC-corrected data (if any). ("Middle" is controlled by PROC WP). Even
    devices that deassert LBUS WITH ECC must provide the data early enough
    to
    avoid synchronizer failure in either of these latches.
    When reading from a microdevice, there is more timing leeway since the
    microcode knows the specific device it is reading from and can use
    a slow-first-half cycle. Also there is no ECC computation. The
    microdevice
    drives the data lines during the first half and the processor
    effectively clocks them at the trailing edge of FIRST HALF (actually
    there
    is one latch open during FIRST HALF followed by a second latch open
    during SECOND HALF; this is done for hardware minimization reasons).
    The device data must be stable early enough to avoid synchronizer
    failure in these latches. The microcode will use a slow-second-half
    cycle if necessary, since it does not see the data until SECOND HALF.
    Lbus data lines not driven by a microdevice will be brought to 1 by
    the terminator, but not quickly enough to avoid problems. Thus all
    microdevice reads must drive at least LBUS 0-33.
    Note that when doing a memory read, the data are driven two clocks
    after the request (skipping LBUS WAIT cycles); the bus-driver enable
    should come from a clocked register. When doing a microdevice read.
    the data are driven by LBUS DEV READ gated by matching of LBUS DEV ADDR
    9-5. LBUS DEV READ takes some time after the beginning of the cycle
    to become stable, and the device should introduce as little additional
    delay as it can. The device should only drive the bus during FIRST HALF,
    so that it turns off in plenty of time before the next cycle.
    When writing into memory from a DMA device, the data, including the ECC
    code added by the memory control, must be stable at the memory chips
    before the leading edge of the clock (which is when WRITE is asserted
    to the RAMs).
    When a cycle is extended because of a trap, so that FIRST HALF happens
    twice,
    the latch through which the processor receives Lbus data is only opened
    during the first FIRST HALF. When a cycle is repeated because of LBUS
    WAIT,
    memory-read data are only received from the bus during the first
    instance
    of the cycle. (This only happens when a block read is done from a device
    that uses LBUS WAIT, since only in a block read can an active cycle and
    a data cycle coincide, and LBUS WAIT is associated with active cycles.)
    Microdevice-write and memory-write data are driven during throughout an
    extended or repeated cycle (microdevice-write data are only driven
    during
    SECOND HALF).
    The leading edge of FIRST HALF does not precede the trailing edge of
    the clock. It is not a good idea to depend on this. The trailing
    edge of FIRST-HALF preceeds the leading edge of the clock.
    LBUS WITH ECC is driven with the same timing requirements as the data
    lines.
    LBUS DEV COND must be stable before the trailing edge of the clock.
    SPY ADDR 5-0 are stable whenever SPY READ or SPY WRITE is asserted.
    The SPY data lines should be clocked by the trailing edge of SPY WRITE,
    and should be driven whenever SPY READ is asserted. If a bidirectional
    transceiver is used to bring the SPY bus onto a board, its direction
    should be controlled by SPY READ, so that it will not glitch at the
    trailing edge of SPY WRITE; the FEP latches the SPY lines before it
    deasserts SPY READ. The FEP allows a long time [?? ns] for a spy
    read or write, so slow logic may be employed on this bus.
    LBUS ADDR 0-11   AA1-12     DP SQ- MC* AU- FEP* BUS
    LBUS ADDR 12-23  AA13-24    MC* AU- FEP* BUS
    U TYPE MAP SEL 0-5
                     AA13-18    DP SQ*
    SPY READ DP ID L AA19       DP SQ*
    U XYBUS SEL      AA20       DP SQ*
    U STKP COUNT     AA21       DP SQ*
    U OBUS COR 0-2   AA22-24    DP SQ*
    U OBUS HTYPE 0-2 AA25-27    DP SQ*
    LBUS ID REQUEST L
                     AA25       MC- AU- FEP* BUS
    LBUS BLOCK REQUEST L
                     AA26       MC* AU- FEP- BUS-
    LBUS DEV READ L  AA27       MC* AU- FEP BUS
    U OBUS LTYPE SEL AA28       DP SQ*
    LBUS DEV WRITE L AA28       MC* AU- FEP BUS
    LBUS DEV COND L  AA29       DP- SQ MC- AU- FEP- BUS*
    FEP CONTINUITY   AA30       DP SQ MC AU FEP*
    Asserted by the FEP and read back on the other continuity lines
    to detect the presence of processor boards (and in the correct slots).
    MC CONTINUITY    AA31       DP- SQ- MC* AU- FEP
    Jumpered to FEP CONTINUITY on the MC card.
    SQ CONTINUITY    AA32       DP- SQ* MC- AU- FEP



    Jumpered to FEP CONTINUITY on the SQ card.
    LBUS 0-29        AC1-30     DP* SQ MC* AU FEP* BUS*
    DP CONTINUITY    AC31       DP* SQ- MC- AU- FEP
    Jumpered to FEP CONTINUITY on the DP card.
    AU CONTINUITY    AC32       DP- SQ- MC- AU* FEP
    Jumpered to FEP CONTINUITY on the AU card.
    SPY 0-7          BA1-8      DP- SQ* MC* FEP* BUS*
    SPY ADDR 0-5     BA9-14     DP- SQ MC AU FEP* BUS
    SPY ADDR 0-1 also used for FEP-DMA
    SPY READ L       BA15       DP- SQ MC AU FEP* BUS
    SPY WRITE L      BA16       DP- SQ MC AU FEP* BUS
    SPY DMA ENB L    BA17       FEP* BUS
    (spare)          BA17       DP- SQ- MC- AU-
    TASK 4 REQ L     BA18       DP- SQ MC- AU- FEP- BUS*
    Low-priority task wakeup
    LBUS DEV 0-9     BA19-28    DP SQ* MC AU- FEP BUS
    U AMWA 0-9
    Note that these lines have two names, since they serve as both the
    Lbus microdevice address and some datapath control signals. The same
    wires are bussed all the way through both the processor and the Lbus.
    LBUS FIRST HALF +,-
                     BA29,BC29  FEP* BUS
    Terminate with 68 ohms to -2 V at end of BUS.
    (spare)          BA29,BC29  DP- SQ- MC- AU-
    TASK 8-9 REQ L   BA30,BC30  DP- SQ MC- AU- BUS*
    (See below; listed here since they fall here in pin order)
    (spare)          BA31       DP- SQ-
    COND             BC31       DP* SQ*
    EXTERNAL REQUEST L
                     BA31       MC- *** BUS*
    EXTERNAL GRANT L BC31       MC* *** BUS-
    Traces between SQ and MC should be cut. These will have
    to be jumpered around the AU and FE slots.
    LBUS CLOCK +,-   BA30,BC30  FEP*
                     BA32,BC32  BUS
    Terminate with 68 ohms to -2 V at end of BUS.
    Note that these signals change pin number at the FEP.
    PROC CLOCK +,-   BA32,BC32  DP SQ MC AU
                     BA31,BC31  FEP*
    (Separately-driven duplicate of LBUS CLOCK.
    Terminate with 68 ohms to -2 V at DP end.
    Note that these signals change pin number at the FEP.
    LBUS 30-35       BC1-6      DP* SQ MC* AU FEP* BUS*
    LBUS 36-43       BC7-14     MC* AU FEP* BUS*
    DP TRANSPORT TRAP L
                     BC7        DP* SQ
    Asserted if a trap is required for garbage-collector processing
    of the data being read from memory (a function of the data type
    and the high-order address field).
    DP TYPE TRAP     BC8        DP* SQ
    Asserted if the type map calls for a trap (bad data type or
    invisible pointer).
    DP TRAP PARAM 0-3
                     BC9-12     DP* SQ
    Trap parameter (dispatch code for arithmetic trap, trap number
    for type trap).
    DP SLOW JUMP L   BC13       DP* SQ
    Asserted if a non-NOPing trap is required (used by the stack
    garbage collector that doesn't exist yet).
    DP MISC TRAP     BC14       DP* SQ
    IOR of trap conditions other than the above.
    LBUS WITH ECC    BC15       MC AU- FEP BUS*
    AMEM PAR ERR L   BC15       DP* SQ
    Parity error in A-memory; stops machine
    (spare)          BC16       DP- SQ- MC- AU- FEP- BUS-
    Spare Lbus line
    LBUS POWER RESET L
                     BC17       DP SQ MC AU FEP* BUS
    Terminate somehow. May need to be brought out to power supply?
    (May go to front panel also, but FEP will provide that connection.)
    TASK 8-15 REQ L  BA30,BC30,BC18-23
                                DP- SQ MC- AU- FEP- BUS*
    TASK 8-9 REQ L are not connected to the FEP.
    LBUS REQUEST L   BC24       MC* AU- FEP* BUS
    TYPE PAR ERR L   BC24       DP* SQ
    Parity error in type map
    LBUS WRITE L     BC25       MC* AU- FEP* BUS
    GC MAP PAR ERR L BC25       DP* SQ
    Parity error in garbage-collector address-space-quantum map
    LBUS REFRESH L   BC26       MC- AU- FEP* BUS
    BMEM PAR ERR L   BC26       DP* SQ
    Parity error in B-memory; stops machine
    LBUS WAIT L      BC27       DP SQ- MC AU- FEP BUS*
    LBUS RESET L     BC28       DP SQ MC AU FEP* BUS
    PROC WP +,-      CA1,CC1    DP SQ MC AU FEP*
    Write-pulse for internal static RAMs; occurs twice per cycle.
    Terminate with 68 ohms to -2 V at DP end.
    PROC FIRST HALF +,-
                     CA2,CC2    DP SQ MC AU FEP*
    Separately-driven duplicate of LBUS FIRST HALF.
    Terminate with 68 ohms to -2 V at DP end.
    CLK EXTEND CYCLE CA3        DP* SQ- MC* AU- FEP
    A wired-OR ECL signal, asserted when extra time is needed for a trap.
    Terminate with 100 ohms to -2 V at DP end and on FEP.
    CLK CS PRESET L  CA4        DP SQ- MC- AU- FEP*
    Forces chip-select for A,B memories on at the beginning of the cycle,
    until there has been enough time for the pass-around decision.
    (Saves a few nanoseconds).
    SQ NEXT INST L   CA5        DP SQ* MC AU- FEP-
    Asserted if this is the last microinstruction for this
    macroinstruction.
    U AMRA 0-5       CA6-11     DP SQ*
    FEP LBUS RQ L    CA6        MC AU- FEP*
    Asserted if FEP wants the bus or is using it (active cycle).
    REFRESH RQ L     CA7        MC AU- FEP*
    Asserted if time for a memory refresh, or refresh active cycle.
    MC ECC DELAY      CA8       MC* AU- FEP
    Extends the clock during the second half in order to provide
    time for single-bit error correction.
    This is an ECL signal.
    DOUBLE ECC ERROR L
                     CA9        MC* AU- FEP
    True if there is an uncorrectable error in the data for this
    memory read.
    (unknown)        CA10-11    MC AU- FEP
    U AMRA 6-11      CA12-17    DP SQ* MC AU(-?)
    U AMRA SEL 0-1   CA18-19    DP SQ* MC AU(-?)
    U AMWA 10-11     CA20-21    DP SQ* MC AU(-?)
    U AMWA SEL 0-1   CA22-23    DP SQ* MC AU(-?)
    U MAGIC 0-3      CA24-27    DP SQ* MC AU
    U SPEC 0-4       CA28-32    DP SQ* MC AU
    CLK WO ENB L     CC3        DP SQ- MC- AU- FEP*
    Another timing signal for A,B memory.
    DP SET GC TAG L  CC4        DP* SQ- MC- AU- FEP
    Registered output from the GC map indicating that the
    Abus datum is a pointer to a temporary space. This sets
    a GC page tag bit if main memory is being written.
     NOP L           CC5        DP SQ* MC AU FEP-
    Asserted if the current microinstruction should not do
    anything, because the processor is stopped, stalled, or
    trapping (valid late, should not be used to gate the clock).
    U SPEED 0-1      CC6-7      DP- SQ* MC- AU- FEP
    CLK EXTRA INNINGS
                     CC8        DP- SQ MC- AU- FEP*
    Asserted during the second cycle of a trap.
    TASK 3 REQ       CC9        DP- SQ MC- AU- FEP*
    Task wakeup from the FEP
    MC PROC NORMAL GRANT L
                     CC10       DP SQ- MC* AU- FEP
    Asserted if the LBUS ADDR lines contain an address derived
    by mapping the VMA to a physical address. This signal enables
    the DP card to capture the mapped address for possible later
    use in addressing A-memory. Also used by the page tag memory.
    PAGE TAG PAR ERR L
                     CC11       DP- SQ MC- AU- FEP*
    Parity error in page tag memory; stops machine.
    SPARE ERROR L    CC12       DP- SQ MC- AU-
    Grounding this halts the machine after completing the current
    microinstruction;
    (spare)          CC13-15    DP- SQ- MC- AU-
    Bus these across processor (except FEP) and maybe we'll
    find a need for them.
    INST 0-7         CC16-23    DP MC*
    Low 8 bits of the current macroinstruction.
    Note: these lines are wired around the SQ slot.
    U AU OP 0-7      CC16-23    SQ* AU
    Microcode control for the AU.
    [This assumes 8 more bits of control memory are wedged in.]
    Note: these lines are wired around the MC slot.
    AU STOP L        CC24       SQ AU*
    Any error on the AU that needs to stop the machine.
    Note: this line is wired around the MC slot.
    (spare)          CC25- 28 SQ- AU-
    Connect these between the SQ and AU for possible future use
    Note: these lines are wired around the MC slot.
    SEQUENCE BREAK   CC24       DP* MC
    Macrocode interrupt request.
    Note: this line is wired around the SQ slot.
    MC COND          CC25       DP MC*
    A microcode skip condition.
    Note: this line is wired around the SQ slot.
    MC OBUS TO LBUS L
                     CC26       DP MC*
    Enables the datapath output to drive the Lbus
    Note: this line is wired around the SQ slot.
    MC OBUS REG TO LBUS L
                     CC27       DP MC*
    Enables the datapath result from the previous microinstruction
    to drive the Lbus (used when writing main memory)
    Note: this line is wired around the SQ slot.
    MC ADDR IN AMEM L
                     CC28       DP MC*
    Indicates that the VMA maps to an A-memory address
    Note: this line is wired around the SQ slot.
    MC ABUS 32-35    CC29-32    DP* SQ- MC* AU*
    Data bus between DP, MC, and AU.
    MC ABUS 0-31     DC1-32     DP*
                     DA1-32     MC* AU*
    Bidirectional data bus between DP, MC, and AU.
    Note: this is wired around the SQ slot.
    Note: this is on the "C" column at the DP, but the "A" column
    elsewhere.
    U BMRA 0-7       DA1-8      DP SQ*
    U BMWA 0-3       DAS-12     DP SQ*
    U BMEM FROM XBUS DA13       DP SQ*
    U COND FUNC 0-1  DA14-15    DP SQ*
    U COND SEL 0-4   DA16-20    DP SQ*
    U BYTE F 0-1     DA21-22    DP SQ*
    U ALU 0-3        DA23-26    DP SQ*
    DISPATCH 0-3     DA27-30    DP* SQ
    Contents of field being dispatched on
    (spare)          DA31-32    DP- SQ-
    (spare)          DC1-4      SQ- MC-
    CUR TASK 0-3     DC5-8      SQ* MC
    Task in which the current microinstruction is executing
    TASK SWITCH L    DC9        SQ* MC
    Asserted if the next microinstruction will be from a different task
    WANT NEXT INST   DC10       SQ* MC
    Asserted if the address supplied by the IFU in the previous cycle
    is actually being used as the next microinstruction address.
    Stalls the processor if the address was not valid after all.
    MC WAIT          DC11       SQ MC*
    Asserted if the processor must stall and wait for the Lbus
    MC MAP MISS L    DC12       SQ MC*
    Asserted if a map-miss trap should be taken
    MC TRAP PARAM 0-1
                     DC13,14    SQ MC*
    Modifiers for trap address
    MC TASK INHIBIT L
                     DC15       SQ MC*
    Inhibits a task switch after the next instruction.
    MC STOP L        DC16       SQ MC*
    Any parity error on MC board; stops processor.
    IFU DISP 2-13    DC18-28    SQ MC*
    Control-memory address of the first microinstruction to execute
    the next macroinstruction
    (spare)          DC29-30    SQ- MC-
    U MEM 2-0        DC17,DC31-32
                                SQ* MC
    Memory-control control field
    Bit 2 is not next to the other bits for historical reasons
    Pins DC1-32 on the AU slot are left unconnected for possible cabling
    to a second board or other expansion.
    Pins CA11-32, CC12-32, DA1-32, DC1-32 on the FEP slot are left
    unconnected
    for paddleboard use.
    __________________________________________________________________________

    ______________________________________
    10:0      Disk. bus.
    11        Obus in
    15:12     SMD: tage 3:0
    19:16     Unit number
    23:20     Command opcode (selects state machine
              program)
    24        Start. Starts state machine if 1. Reads
              back as -DISK IDLE (1 if state machine
              running).
    28:25     Task. 8-15 selects that task, otherwise no
              task.
    29        FEP using disk. Enables SPY bus DMA.
    30        32-bit mode (forces fixnum data type in high
              bits)
    31        (spare)
    ______________________________________

    ______________________________________
           0           Read clock
           1           Servo clock
           2           Read data
           3           Index
           4           Sector
           7:5         (spare)
    ______________________________________

    ______________________________________
    0     Paddle ID enable (paddleboard IO prom to disk bus)
    1     Paddle disk enable (disconnect disk part of
          paddle board)
    2     Paddle net enable (disconnect network part of
          paddle board)
    3     Paddle power OK (enable disk to spin up)
    ______________________________________

    ______________________________________
    10:0          Error pattern
    15:11         Bit number within the word
    ______________________________________

    ______________________________________
           9:5       card slot number
           4:3       subdevice (0-disk)
           2:0       operation
    ______________________________________

    ______________________________________
    0        write disk buffer directly (rev 2 and later)
    1        dma cycle (start dma cycle without dismission)
    2        dismiss, task acknowledge (just clear wakeup)
    3        dismiss & dma cycle
    4        dismiss (only)
    5        kill disk task
    6        dismiss, task acknowledge, set end flag
    7        dma cycle & set end flag & dismiss
    ______________________________________

    ______________________________________
    9:5        card slot number
    4:3        subdevice (0-disk)
    2:0        operation (0 for disk - read data buffer).
    ______________________________________